View V62C1804096_1333861.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

V62C1804096 512K X 8, CMOS STATIC RAM
PRELIMINARY
s s s s s s s s
Row Decoder
1024 x 4096
Sense Amp
CILETIV LESOM
Features
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
Description
The V62C1804096 is a very low power CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW CE1, and active HIGH CE2, an active LOW OE, and three static I/O's. This device has an a u to m a tic p o w e r -d o w n mo d e f e a tu r e w h e n deselected.
High-speed: 85, 100 ns Ultra low standby current of 2A (max.) Fully static operation All inputs and outputs directly compatible Three state outputs Ultra low data retention current (VCC = 1.0V) Operating voltage: 1.8V-2.3V Packages - 36-Ball CSP BGA (8mm x 10mm)
Functional Block Diagram
Input Buffer I/O8
I/O1
Column Decoder A10 A11 A12 A13 A14 A15 A16 A17 A18
Control Circuit
OE WE CE1 CE2
Device Usage Chart
Operating Temperature Range 0C to 70 C -40C to +85C Package Outline B * * Access Time (ns) 85 * * 100 * * L * Power LL * * Temperature Mark Blank I
V62C1804096 Rev. 1.0 October 2001
1
V62C1804096
WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip enabled, when WE is HIGH and OE is LOW, output data will be present at the I/O pins; when WE is LOW and OE is HIGH, the data present on the I/O pins will be written into the selected memory locations. I/O1-I/O8 Data Input and Data Output Ports These 8 bidirectional ports are used to read data from and write data into the RAM. VCC GND Power Supply Ground
CE1, CE2 Chip Enable Inputs CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The I/O pins will be in the high-impedance state when deselected. OE Output Enable Input The Output Enable input is active LOW. With chip enabled, when OE is LOW and WE HIGH, data of the selected memory location will be available on the I/O pins. When OE is HIGH, the I/O pins will be in the high impedance state.
CILETIV LESOM
Pin Descriptions
A 0-A18 Address Inputs These 19 address inputs select one of the 512K x 8 bit segments in the RAM.
1 A B C D E F G H 2 3 4 5 6 TOP VIEW
V62C1804096 Rev. 1.0 October 2001
Pin Configurations (Top View)
36 BGA
1 A B C D E F G H A0 I/O5 I/O6 VSS VCC I/O7 I/O8 A9 2 A1 A2 NB NB NB NB OE A10 3 CE2 WE NC NB NB A18 CE1 A11 4 A3 A4 A5 NB NB A17 A16 A12 5 A6 A7 NB NB NB NB A15 A13 6 A8 I/O1 I/O2 VCC VSS I/O3 I/O4 A14
Note: NC means no connect. NB means no ball. TOP VIEW
2
V62C1804096
CILETIV LESOM
V
MOSEL-VITELIC MANUFACTURED 62 = STANDARD
Part Number Information
62 C
1 18 80 8
4096
-
TEMP.
SRAM FAMILY
OPERATING VOLTAGE
DENSITY PWR. 4096K SPEED 85 ns 100 ns
PKG
BLANK = 0C to 70C I = -40C to +85C
C = CMOS PROCESS 18 = 1.8V-2.3V 1 ORGANIZATION
80 8 = 8-bit
T = TSOP STANDARD B = BGA
L = LOW POWER LL = LOW LOW POWER
Absolute Maximum Ratings (1)
Symbol
VCC VN V DQ TBIAS TSTG
Parameter
Supply Voltage Input Voltage Input/Output Voltage Applied Temperature Under Bias Storage Temperature
Commercial
-0.5 to + VCC + 0.5 -0.5 to + VCC + 0.5 VCC + 0.3 -10 to +125 -55 to +125
Industrial
-0.5 to + VCC + 0.5 -0.5 to + VCC + 0.5 VCC + 0.3 -65 to +135 -65 to +150
Units
V V V C C
NOTE: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance*
TA = 25C, f = 1.0MHz
Symbol C IN C OUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VI/O = 0V Max. 6 8 Unit pF pF
Truth Table
Mode
Standby Standby Output Disable Read Write
CE 1
H X L L L
CE2
X L H H H
OE
X X H L X
WE
X X H H L
I/O Operation
High Z High Z High Z DOUT DIN
NOTE: 1. This parameter is guaranteed and not tested.
NOTE: X = Don't Care, L = LOW, H = HIGH
V62C1804096 Rev. 1.0 October 2001
3
V62C1804096
NOTES: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. VIL (Min.) = -3.0V for pulse width < tRC /2. 3. Maximum value.
CILETIV LESOM
Symbol
VIL VIH IIL IOL VOL V OH
DC Electrical Characteristics (over all temperature ranges, VCC = 1.8V-2.3V)
Parameter
Input LOW Voltage(1,2) Input HIGH Voltage(1) Input Leakage Current Output Leakage Current Output LOW Voltage Output HIGH Voltage VCC = Max, VIN = 0V to VCC VCC = Max, CE1 = VIH , VOUT = 0V to VCC VCC = Min, IOL = 2mA VCC = Min, IOH = -0.5mA
Test Conditions
Min.
-0.3 1.6 -- -- -- VCC -0.4
Typ.
-- -- -- -- -- --
Max.
0.4 VCC+0.3 1 1 0.4 --
Units
V V A A V V
Symbol
ICC1
Parameter
Average Operating Current, CE1 = VIL, CE2 = VCC - 0.2, Output Open, V CC = Max. TTL Standby Current CE1 >=VIH , CE2 <= VIL, VCC = Max., f = 0 CMOS Standby Current, CE1 S VCC - 0.2V, CE2 0.2V, V IN>= VCC - 0.2V or VIN <=0.2V, VCC = Max., f = 0 f = fmax f = 1 MHz L LL L LL
Comm.(3)
25 2 0.4 0.3 5 2
Ind.(3)
30 3 0.5 0.3 7 3
Units
mA
ISB
mA
ISB1
A
AC Test Conditions
Input Pulse Levels Input Rise and Fall Times Timing Reference Levels Output Load 0 to 1.6V 5 ns 0.9V see below
AC Test Loads and Waveforms
CL*
TTL
CL = 30pF + 1TTL Load * Includes scope and jig capacitance
V62C1804096 Rev. 1.0 October 2001
4
V62C1804096
NOTES: 1. tRC = Read Cycle Time 2. TA = +25C.
CILETIV LESOM
Symbol
VDR
Data Retention Characteristics
Parameter
VCC for Data Retention CE1 VCC - 0.2V, CE2 < 0.2V, VIN VCC - 0.2V, or VIN 0.2V Data Retention Current CE1 VDR - 0.2V, CE2 < 0.2V, VIN VCC - 0.2V, or VIN 0.2V, VDR = 1.0V Com'l L LL Ind. L LL tCDR tR Chip Deselect to Data Retention Time Operation Recovery Time (see Retention Waveform)
Power
Min.
1.0
Typ.(2)
--
Max.
2.3
Units
V
ICCDR
-- -- -- -- 0 tRC(1)
1 0.5 -- -- -- --
3 1.5 5 2 -- --
A
ns ns
Low VCC Data Retention Waveform (1) (CE1 Controlled)
Data Retention Mode VCC 1.8V tCDR CE1 1.6V CE1 VCC - 0.2V VDR 1V tR 1.6V 1.8V
Key to Switching Waveforms
WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM H TO L OUTPUTS WILL BE STEADY WILL BE CHANGING FROM H TO L WILL BE CHANGING FROM L TO H CHANGING: STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE "OFF" STATE
MAY CHANGE FROM L TO H
DON'T CARE: ANY CHANGE PERMITTED DOES NOT APPLY
V62C1804096 Rev. 1.0 October 2001
5
V62C1804096
CILETIV LESOM
Read Cycle
Parameter Name
tRC tAA tACS1 tACS2 tOE tCLZ1 tCLZ2 tOLZ tCHZ tOHZ tOH
AC Electrical Characteristics
(over all temperature ranges)
85 Parameter
Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable Access Time Output Enable to Output Valid Chip Enable to Output in Low Z Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change
100 Max.
-- 85 85 85 85 -- -- -- 30 30 --
Min.
85 -- -- -- -- 10 10 5 -- -- 10
Min.
100 -- -- -- -- 15 15 10 -- -- 10
Max.
-- 100 100 100 40 -- -- -- 35 35 --
Unit
ns ns ns ns ns ns ns ns ns ns ns
Write Cycle
Parameter Name
tWC tCW tAS tAW tWP tWR tWHZ tDW tDH
85 Parameter
Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output High-Z Data Setup to End of Write Data Hold from End of Write
100 Max.
-- -- -- -- -- -- 25 -- --
Min.
85 70 0 70 60 5 -- 40 0
Min.
70 60 0 60 50 5 -- 45 0
Max.
-- -- -- -- -- -- 30 -- --
Unit
ns ns ns ns ns ns ns ns ns
V62C1804096 Rev. 1.0 October 2001
6
V62C1804096
NOTES: 1. WE = VIH. 2. CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE1 transition LOW and/or CE2 transition HIGH. 4. OE = VIL. 5. Transition is measured 500mV from steady state with CL = 5pF. This parameter is guaranteed and not 100% tested.
CILETIV LESOM
Read Cycle 1(1, 2)
ADDRESS OE I/O
Switching Waveforms (Read Cycle)
tRC
tAA
tOE tOLZ
tOH tOHZ(5)
Read Cycle 2(1, 2, 4)
tRC ADDRESS tAA tOH I/O tOH
Read Cycle 3(1, 3, 4)
ADDRESS
CE1 tACS1 CE2 tACS2 tCLZ1(5) tCLZ2(5)
tCHZ(5)
I/O
V62C1804096 Rev. 1.0 October 2001
7
V62C1804096
NOTES: 1. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 2. tWR is measured from the earlier of CE1 or WE going high, or CE2 going LOW at the end of the write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 4. OE = VIL or VIH. However it is recommended to keep OE at VIH during write cycle to avoid bus contention. 5. If CE1 is LOW and CE2 is HIGH during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 6. tCW is measured from CE1 going low or CE2 going HIGH to the end of write.
CILETIV LESOM
ADDRESS CE1 CE2 WE OUTPUT INPUT ADDRESS CE1 CE2 WE OUTPUT INPUT
V62C1804096 Rev. 1.0 October 2001
Switching Waveforms (Write Cycle)
Write Cycle 1 (WE Controlled)(4)
tWC
tWR(2) tCW(6)
tAW tCW(6) tAS
tWP(1)
tWHZ
tDW
tDH
Write Cycle 2 (CE Controlled)(4)
tWC
tCW(6)
(4)
tWR(2)
tAW tCW(6) tAS
High-Z tDW tDH
(5)
8
V62C1804096
e
E1
E
A
C
aaa SIDE VIEW
V62C1804096 Rev. 1.0 October 2001
9
A1
CILETIV LESOM
Package Diagrams
36 Ball--8x10 BGA
D D1 A A1 6 5 4 3 2 1 A B C D E F G H b c D D1 E E1 e aaa BOTTOM VIEW b SOLDER BALL
SYMBOL
UNIT.MM 1.05+0.15 0.250.05 0.35.0.05 0.30(TYP) 10.000.10 5.25 8.000.10 3.75 0.75TYP 0.10
WORLDWIDE OFFICES
TAIWAN
7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888
V62C1804096
UK & IRELAND
SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516
U.S.A.
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
NORTHWESTERN
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC
CILETIV LESOM
SINGAPORE
10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013
JAPAN
ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402
GERMANY (CONTINENTAL EUROPE & ISRAEL)
BENZSTRASSE 32 71083 HERRENBERG GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22
U.S. SALES OFFICES
SOUTHWESTERN
302 N. EL CAMINO REAL #200 SAN CLEMENTE, CA 92672 PHONE: 949-361-7873 FAX: 949-361-7807
CENTRAL, NORTHEASTERN & SOUTHEASTERN
604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 214-352-3775 FAX: 214-904-9029
(c) Copyright , MOSEL VITELIC Inc.
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

▲Up To Search▲

Price & Availability of V62C1804096

	To Download V62C1804096 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .